1. Field of the Invention
The present invention relates generally to drive circuits for a power device of a power driving stage, and, more particularly, to a driver circuit operating from a supply voltage (e.g. a charge pump voltage) that is higher than the supply voltage of the power device.
2. Description of Related Art
A driver circuit is generally a relatively low power circuit that drives, or controls, a higher power device. The power device may be part of a power driving stage for a load. An example is a load that is a motor, such as a brushless motor, that provides the motive force for a spindle of a hard disk drive. Similar driver circuits are applied elsewhere, such as in voice coil motor (VCM) systems.
One of the most widely used types of driver circuits in such applications uses a three-phase brushless motor in a configuration in which current energizes respective motor coils using a full wave bridge configuration. The bridge includes two power stages for each phase, so typically there are six power stages, each with a power device. Three of the power stages, and their power devices, are referred as being “low side” stages and devices because they are connected between a motor coil and ground. The other three of the power stages, and their power devices, are referred to as “high side” stages and devices because they are connected between a power supply and a motor coil.
The power devices are operated as switches in a sequence that allows pulses of current to flow from the power supply through a high side power device, a coil of a first of the three stages, a coil of a second of the three stages, and then through a low side power device to ground. This process is repeated in a generally well known manner for the other power devices and coil pairs to achieve three phase energization from a single, direct current, power supply. The switching, or commutation, characteristics of the power devices are very important in achieving good performance from the motor and other favorable characteristics.
Control of the switching of the power devices is performed by a driver circuit for each power device. In the typical use described above with six power stages, there are three low side drivers and three high side drivers. The power devices may be of a variety of electronic switch devices and the driver circuits are configured suitably for the power devices. Power devices of general application to hard disk drivers, and the like, are each often an MOS (metal-oxide-semiconductor) FET (field effect transistor). One type of such transistors of considerable interest is referred to as a DMOS transistor (double diffusion MOS).
DMOS devices can be readily integrated in chips with other circuitry, including power control circuitry. So it is attractive to have an entire set of drive stages, including all the power devices and all the driver circuits for the power devices, in one chip.
Even where all the power devices are alike, e.g. N channel DMOS devices, it is generally the case that the high side drivers differ from the low side drivers because high side drivers for such power devices often require a voltage, referred to as a charge pump voltage or boost voltage, at a higher voltage level than that supplied by the power supply for the power stages. By known techniques, a charge pump voltage may be generated from the supply voltage and used by all of the high side drivers. Such an auxiliary supply if present, however, is power limited; the desired voltage can be supplied but at a modest current level.
The field of motion control using integrated signal and power components, the respective requirements of low and high side drivers, and the characteristics sought in applications of motor drivers are described more fully in Smart Power ICs, by B. Murari et al;, Eds., 1995, particularly Chapter 5, “Motion Control” by R. Gariboldi, at pp. 225-283, which is herein incorporated by reference for its description of background to the present invention.
As is disclosed, for example from the above-mentioned Gariboldi publication, for applications such as hard disk drives it is of utmost importance to control the output voltage slope in order to reduce electromagnetic interference (EMI). Generally, the slope is desired to be steep, but not so abrupt as to cause any appreciable noise. Drive circuits have therefore generally included slew rate control circuits to achieve fast, smooth transitions.
In a typical slew rate control system, a capacitor is charged and discharged by two current generators. Preferably, one wishes to have the same smooth, linear commutation both in going off-to-on and on-to-off. Also, one wishes to have the gate voltage change over a range from ground, or zero, to the maximum supply voltage, or at least a voltage that assures full turn-on of the power device. The circuitry for doing so is referred to as a voltage ramp generator. It can be achieved, by typical integration techniques, using basic current mirrors, one of a pair of matched PNP bipolar transistors on the high side of the drive and the other of a pair of matched NPN bipolar transistors on the low side of the drive. Each pair of the transistor structures has one with a base-collector connection so the device acts as a diode. The diode is connected to the base of the other matched transistor. In some applications, this can produce good linearity for much of the supply voltage range, but is limited by collector-emitter saturation voltages near ground and near the positive voltage. Generally, problems in achieving the desired linearity increase as the supply voltage is increased. The greater precision with which linearity is achieved means that less noise can occur to affect the driver or its load.
An approach for attaining linearity at higher voltages than that for which the basic current mirror is suitable would be to use cascoded current mirrors. A description of basic cascoded current mirrors and their use in constant-current stages is contained, for example, in Bipolar and MOS Analog Integrated Circuit Design by Alan B. Grebene, Sec. 4.1, pp. 170-183, which is herein incorporated by reference. However, a single cascoded solution is not effective because it is not capable of ramping down to zero volts. The PN junction effects of the cascode-connected transistors mean an inherent higher lower voltage limit. The inability to go to zero volts is unacceptable for a high performance drive.
Similar problems are encountered with current mirrors or cascoded current mirrors made up of MOSFET (metal-oxide-semiconductor-field-effect-transistor) devices. Basic MOSFET current mirrors are also limited as far as providing good linearity in ramping with voltages encountered in integrated circuit charge pump supplies. Cascode connected MOSFETs provide a better degree of linearity but lack the ability to ramp down to a zero level to ensure turn off of a power device. There are inherent gate to source voltage drops of MOSFETs that prevent a satisfactory reduction in voltage. The book of Grebene cited above also describes the nature and use of MOSFET current mirrors, at Sec. 6.2, pp. 271-277, and is herein incorporated by reference.
Referring now to FIG. 1, a circuit schematic diagram of a representative prior art voltage ramp generator is shown. A DC supply of a voltage Vcc is applied across a combination of current generators and a capacitor C, which may, for example, be a slew rate control capacitor of a driver circuit. The current generators, also referred to as constant current sources, include a first current source Ic that is connected between the supply and the capacitor C for charging the capacitor. A second current source Id for discharging the capacitor C is connected to the capacitor's high side or charge terminal, as is source Ic, and to ground. A switch Sw1 is connected in a position to make or break a connection between source Ic and the capacitor C. Switch Sw1 is activated by command logic signals (COM) applied from other circuitry. A switch Sw2 is connected to make or break a connection between source Id and capacitor C; it receives command signals through an inverter connected to the COM signals.
When a command signal is received to close Sw1, source Ic will charge up the capacitor to an elevated voltage near Vcc while Sw2 remains open. When a command signal is received to open Sw1, Sw2 closes and source Id will discharge C. Source Ic and source Id can each be designed to carry currents sufficient to provide substantially matching slew rates for the capacitor voltage Vout. For example, Ic and Id may each be designed to conduct a current of magnitude I. The slew rate or slope of the capacitor voltage Vout is therefore I/C both during charging and discharging.
FIG. 2 illustrates a further example of a prior art voltage ramp generator and is a more specific example of the general configuration of FIG. 1. Relating the elements to FIG. 1, a current source Ic connected to a pair of matched PNP transistor structures Q1 and Q2 connected as a basic current mirror between the supply Vcc and capacitor C. Transistor Q1 has a direct connection between its base and collector and operates as a diode. A discharging current source Id connected to a pair of matched NPN transistor structures Q3 and Q4, which are also connected as a basic current mirror in which Q3 has its collector and based connected to operate as a diode.
In the drawings, a symbol in the form of a pair of overlapping circles is used to represent a current source and to inform one that in addition to the illustrated transistors, there are resistors and/or other elements for transistor biasing in accordance with known current source practice. The switches shown in the drawings may be suitable semiconductor switches, such as field effect transistors, in accordance with known practice.
FIG. 3 shows an example of performance sought to be realized by voltage ramp generators like those of FIG. 2. Part A of FIG. 3 shows changes in Vout occurring as a result of command signals (COM) shown in part B on the same time axis. A command signal is either a logic “0” or “1.” Here a “0” command is the signal to start discharging. The signal at time t(0) starts that process. The slew rate of Vout is I/C, where I is the current of source Id. At time t1 the discharge is completed and Vout remains zero until a command signal of “1” is received at time t2. That starts the charging process with substantially the same slope of slew rate, but one determined by the current of source Ic. At time t3, Vout is at its maximum. Vout remains at that level until a further “0” command is received at time t4 and the discharge process begins again.
FIG. 3 is not intended to show exact values of capacitor voltage Vout. For circuits such as FIG. 2, a maximum Vout is not quite the supply voltage Vcc but is equal to Vcc minus a collector-emitter saturation voltage (e.g., for Q2 of FIG. 2) of Vcesat. The minimum Vout is above ground voltage by an amount equal to the collector-emitter saturation voltage (e.g. for Q4 of FIG. 2). The results achieved in FIG. 2 are generally suitable for driver circuits. The minimum Vout is effectively “zero” and sufficient to enable turning off a power device despite the voltage difference mentioned above.
As described above, the operation of some power stages requires a driver circuit operating from a voltage elevated above the power device supply Vcc, such as by about 10v. The elevated charge pump voltage Vcp, can be generated in an integrated circuit from Vcc by known techniques. The higher voltage makes basic current mirrors like those of FIG. 2 perform their ramping functions with a less linear characteristic. In a straightforward integrated circuit design, the imposition of higher voltages on current sources could lead one to change from basic current mirrors as in FIG. 2 to cascode connected current mirrors. In contrast to FIG. 2 having a current mirror with transistor structures such as Q1 and Q2 in a current source, one could have two cascoded current mirrors in each current source both for charging and discharging. The extra transistors of the additional current mirrors are not appreciably difficult to integrate so the ability to achieve good linearity with higher output voltage may initially make cascoded current mirrors appear successful in satisfying the need of high performance driver circuits.
Operating of a voltage ramp generator with cascoded current mirrors, with for example a voltage Vcp about 10 v. higher than Vcc, is generally the same as the generator of FIG. 2 but with a serious drawback. The maximum voltage is not a major problem; ramping up to a voltage close enough to Vcp can usually be readily achieved. However, the minimum voltage is a serious problem. There should be no appreciable voltage at the minimum (i.e. Vout should be substantially “zero” in order to completely turn off the power device being driven). The extra voltage drop introduced by the cascoded current mirrors, as compared to a basic configuration as in FIG. 2, can be enough to prevent turn-off of the power device.
U.S. Pat. No. 5,825,218 issued on Oct. 20, 1998 to Colli et al., which is herein incorporated by reference in its entirety, addresses these concerns with a voltage ramp generator for a driver circuit that is designed to produce a capacitor output voltage Vout that is highly linear between zero and a maximum voltage. Two current sources are employed, one cascoded and one not cascoded; a comparator makes a decision to switch from the first, cascoded current source to the second current source when the capacitor output voltage Vout goes low enough. The first current source takes the capacitor voltage to a low value but not all the way down to ground. When the comparator makes the decision to switch, the second current source then takes the capacitor voltage Vout substantially to zero (ground).
While this approach of U.S. Pat. No. 5,825,218 achieves a linear slope of Vout between the maximum voltage and ground, there is the possibility of having a difference in slopes at the switch-over point due to the fact that two separate current sources are being used. There is no teaching in the U.S. Pat. No. 5,825,218 patent on how such a matching error could be suppressed.
In addition to this concern with mismatch in slopes at the switch-over point between two current sources, a second linearity term of interest is caused by one transistor of a current mirror being in saturation while the other transistor of the current mirror is not. This issue is of concern in U.S. Pat. No. 5,825,218 as well as other prior art circuits. While the voltage ramp generator of U.S. Pat. No. 5,825,218 generally provides a highly linear ramp down of Vout towards ground, there is characteristically a slight deviation from linearity in the ramp as the ramp voltage Vout approaches ground. This linearity error by the mismatch in operating regions between the reference and mirror transistors of a current mirror; as Vout is lowered, the mirror transistor may move from the saturation region into the linear region while the reference transistor of the current mirror remains in the saturated region of operation. As the mirror transistor goes into the triode, or linear, region, its drain current decreases, thereby causing the capacitor to discharge at a slower rate. It is this slower rate of discharge of the capacitor that causes the linearity deviation.